On random wiring in practicable folded clos networks for modern datacenters

Abstract: Big scale, high performance and fault-tolerance, low-cost and graceful expandability are pursued features in current datacenter networks (DCN). Although there have been many proposals for DCNs, most modern installations are equipped with classical folded Clos networks. Recently, regular random topologies, as the Jellyfish, have been proposed for DCNs. However, their completely unstructured nature entails serious design problems. In this paper we propose Random Folded Clos (RFC) and Hydra networks in which the interconnection between certain switches levels is made randomly. Both RFCs and Hydras preserve important properties of Clos networks that provide a straightforward deadlock-free multi-path routing. The proposed networks leverage randomness to be gracefully expandable, thereby allowing for fine grain upgrading. RFCs and Hydras are compared in the paper, in topological and cost terms, against fat-trees, orthogonal fat-trees and random regular networks. Also, experiments are carried out to simulate their performance under synthetic traffic patterns emulating common loads present in warehouse scale computers. These theoretical and empirical studies reveal the interest of these topologies, concluding that Hydra constitutes a practicable alternative to current datacenter networks since it appropriately balance all the main design requirements. Moreover, Hydras perform better than the fat-trees, their natural competitor, being able to connect the same or more computing nodes with significant lower cost and latency while exhibiting comparable throughput. © 1990-2012 IEEE.


Editorial: IEEE Computer Society

 Fecha de publicación: 01/09/2018

Nº de páginas: 14

Tipo de publicación: Artículo de Revista

DOI: 10.1109/TPDS.2018.2805344

ISSN: 1045-9219,1558-2183

Proyecto español: TIN2016-76635-C2-2-R

Proyecto europeo: info:eu-repo/grantAgreement/EC/H2020/671697/EU/MONT-BLANC 3, European scalable and power efficient fpc platform based on low-power embedded technology/MONT-BLANC 3/

Url de la publicación: https://doi.org/10.1109/TPDS.2018.2805344