Abstract: This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.

Autoría

Descargar referencia