Performance characterization of popular DNN models on out-of-order CPUs

Conference object

2023 32nd International Conference on Parallel Architecture and Compilation Techniques: PACT 2023: Vienna, Austria, 21-25 October 2023: proceedings

 Authorship: PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, JOSE ANGEL GREGORIO MONASTERIO, VALENTIN PUENTE VARONA

 2023

Herramienta para la identificación de los cuellos de botella en microarquitecturas de GPUs

Conference object

Avances en arquitectura y tecnología de computadores : Actas de las Jornadas SARTECO 2022

 Authorship: ALVARO SAIZ FERNANDEZ, PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, JOSE ANGEL GREGORIO MONASTERIO, VALENTIN PUENTE VARONA

 2022

Top-down performance profiling on NVIDIA's GPUs

Conference object

2022 IEEE 36th International Parallel and Distributed Processing Symposium: proceedings

 Authorship: ALVARO SAIZ SANCHEZ, PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, JOSE ANGEL GREGORIO MONASTERIO, VALENTIN PUENTE VARONA

 2022

BenchCast: meta-benchmarking para evaluación de rendimiento del procesador

Conference object

Avances en arquitectura y tecnología de computadores: Actas de las Jornadas SARTECO 20/21. Málaga, 21 a 24 de Septiembre de 2021

 Authorship: PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, JOSE ANGEL HERRERO VELASCO, JOSE ANGEL GREGORIO MONASTERIO, VALENTIN PUENTE VARONA

 2021

Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking

Article

IEEE Transactions on Parallel and Distributed Systems, Vol. 32, N. 12, December 2021

 Authorship: PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, JOSE ANGEL GREGORIO MONASTERIO, VALENTIN PUENTE VARONA

 17/05/2021

SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads

Conference object

Proceedings of the 49th International Conference on Parallel Processing, Edmonton, Canada, August 17-20, 2020

 Authorship: PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, JOSE ANGEL HERRERO VELASCO, JOSE ANGEL GREGORIO MONASTERIO, VALENTIN PUENTE VARONA

 2020

Architecting Racetrack Memory preshift through pattern-based prediction mechanisms

Conference object

2019 IEEE 33rd International Parallel and Distributed Processing Symposium : IPDPS 2019 : Proceedings, 20-24 May 2019, Rio de Janeiro, Brazil

 Authorship: ADRIAN COLASO DIEGO, PABLO PRIETO TORRALBO, PABLO ABAD FIDALGO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 2019

Memory hierarchy characterization of NoSQL applications through full-system simulation

Article

IEEE Transactions on Parallel and Distributed Systems (2018), Vol.29, N.5, pp.1161-1173

 Authorship: ADRIAN COLASO DIEGO, PABLO PRIETO TORRALBO, JOSE ANGEL HERRERO VELASCO, PABLO ABAD FIDALGO, LUCIA GREGORIO MENEZO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 01/05/2018

Precisión vs. Coste Computacional en la Simulación de Sistemas Distribuidos

Conference object

Avances en arquitectura y tecnología de computadores : actas de las Jornadas SARTECO, 12-14 sept., Teruel

 Authorship: ADRIAN COLASO DIEGO, PABLO PRIETO TORRALBO, JOSE ANGEL HERRERO VELASCO, PABLO ABAD FIDALGO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 2018

AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory

Article

IEEE Transactions on Parallel and Distributed Systems, Vol. 27, Iss. 1 (1 2016)

 Authorship: PABLO ABAD FIDALGO, PABLO PRIETO TORRALBO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 01/01/2016

Energy minimization at all layers of the data center : The ParaDIME project

Book part

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition : DATE 2016

 Authorship: OSCAR PALOMAR, SANTOSH RETHINAGIRI, GULAY YALCIN, RUBEN TITOS-GIL, PABLO PRIETO TORRALBO

 2016

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Article

Microprocessors and Microsystems 39 (2015) 1174–1189

 Authorship: SANTHOSH KUMAR RETHINAGIRI, OSCAR PALOMAR, ANITA SOBE, GULAY YALCIN, THOMAS KNAUTH, RUBÉN TITOS GIL, PABLO PRIETO TORRALBO, MALTE SCHNEEGAß, ADRIAN CRISTAL, OSMAN UNSAL, PASCAL FELBER, CHRISTOF FETZER, DRAGOMIR MILOJEVIC

 2015

Improving last level shared cache performance through mobile insertion policies (MIP)

Article

ParallelComputing49(2015)13–27

 Authorship: PABLO ABAD FIDALGO, PABLO PRIETO TORRALBO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 01/11/2015

Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs

Conference object

2013 Euromicro Conference on Digital System Design (DSD) : Proceedings

 Authorship: PABLO ABAD FIDALGO, PABLO PRIETO TORRALBO, LUCIA GREGORIO MENEZO, ADRIAN COLASO DIEGO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 2013

CMP off-chip bandwidth scheduling guided by instruction criticality

Conference object

ICS '13: Proceedings of the 27th international ACM conference on International Conference on Supercomputing, 10-14 June, Eugene, Oregón

 Authorship: PABLO PRIETO TORRALBO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 2013

BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip

Conference object

IEEE 30th International Conference on Computer Design (ICCD),September 30 - October 3, 2012 Montreal, Quebec, Canada

 Authorship: PABLO ABAD FIDALGO, PABLO PRIETO TORRALBO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 2012

TOPAZ: An open-source interconnection network simulator for chip multiprocessors and supercomputers

Conference object

Proceedings of the 6 th IEEE/ACM International Symposium on Networks-on-Chip NoCS 2012, 9-11 May, Copenhagen, Denmark

 Authorship: PABLO ABAD FIDALGO, PABLO PRIETO TORRALBO, LUCIA GREGORIO MENEZO, ADRIAN COLASO DIEGO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 2012

Multilevel cache modeling for chip-multiprocessor systems

Article

IEEE Computer Architecture Letters, 2011, 10(2), 49-52

 Authorship: PABLO PRIETO TORRALBO, VALENTIN PUENTE VARONA, JOSE ANGEL GREGORIO MONASTERIO

 01/12/2011

DISEÑO DE UN BACKEND DE PROCESADOR DE PROPÓSITO GENERAL APROPIADO PARA APLICACIONES EMERGENTES Proyecto PID2022-139664NB-I00 financiado por MICIU/AEI /10.13039/501100011033 y por FEDER, UE

 Computer Engineering

 DEPARTAMENTO DE INGENIERÍA INFORMÁTICA Y ELECTRÓNICA

Head: PABLO ABAD FIDALGO

Typology: Competitive national public projects

Start year: 2023

POLÍTICAS Y MECANISMOS ARQUITECTURALES PARA LA MEJORA DE RENDIMIENTO DE APLICACIONES DE APRENDIZAJE AUTOMATIZADO. Proyecto PID2019-110051GB-I00 financiado por MICIU/AEI /10.13039/501100011033

 Computer Engineering

 DEPARTAMENTO DE INGENIERÍA INFORMÁTICA Y ELECTRÓNICA

Head: JOSE ANGEL GREGORIO MONASTERIO

Typology: Competitive national public projects

Start year: 2020

ARQUITECTURAS HETEROGÉNEAS ORIENTADAS A COMPUTACIÓN COGNITIVA (TIN2016-80512-R) (AEI/FEDER, UE)

 Computer Engineering

 DEPARTAMENTO DE INGENIERÍA INFORMÁTICA Y ELECTRÓNICA

Head: VALENTIN PUENTE VARONA

Typology: Competitive national public projects

Start year: 2016

JERARQUIA DE MEMORIA ESCALABLE EN SISTEMAS MANY-CORE CMP (TIN2010-18159)

 Arquitectura Y Tecnología De Computadores

 DEPARTAMENTO DE INGENIERÍA INFORMÁTICA Y ELECTRÓNICA

Head: VALENTIN PUENTE VARONA

Typology: Competitive national public projects

Start year: 2011

Encaminador de mensajes para redes de interconexión de sistemas multiprocesador

Inventor: PABLO ABAD FIDALGO, JOSE ANGEL GREGORIO MONASTERIO, PABLO PRIETO TORRALBO, VALENTIN PUENTE VARONA

Protection: P200701403

Application date: 10/05/2007

Publication or award date: 19/01/2010