Información del personal investigador

Euro-Par 2017: Parallel Processing: 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28 - September 1, 2017: Proceedings

Autoría: ESTEBAN STAFFORD FERNANDEZ, BORJA PEREZ PAVON, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO, MATEO VALERO CORTES

2017

Extending OmpSs for OpenCL Kernel Co-Execution in Heterogeneous Systems

Comunicación a Congreso

2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

Autoría: BORJA PEREZ PAVON, ESTEBAN STAFFORD FERNANDEZ, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO, SERGI MATEO, XAVIER TERUEL, XAVIER MARTORELL, EDUARD AYGUADÉ

2017

Towards co-execution of massive data-parallel OpenCL kernels on CPU and Intel Xeon Phi

Comunicación a Congreso

Proceedings of the International Conference on Computational and Mathematical Methods in Science and Engineering CMMSE-2017: Costa Ballena (Rota), Cádiz, Spain), July 4-8 2017

Autoría: RAUL NOZAL GONZALEZ, BORJA PEREZ PAVON, JOSÉ LUIS BOSQUE ORERO

2017

To distribute or not to distribute : the question of load balancing for performance or energy

Comunicación a Congreso

Avances en arquitectura y tecnología de computadores : actas de las Jornadas SARTECO 2017 : Málaga, 19 a 22 de septiembre

Autoría: ESTEBAN STAFFORD FERNANDEZ, BORJA PEREZ PAVON, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO, MATEO VALERO CORTES

2017

Assessing the Suitability of King Topologies for Interconnection Networks

Artículo de Revista

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 27, NO. 3, P. 682-694 (2016)

Autoría: ESTEBAN STAFFORD FERNANDEZ, JOSÉ LUIS BOSQUE ORERO, MARIA DEL CARMEN MARTINEZ FERNANDEZ, FERNANDO VALLEJO ALONSO, JULIO RAMON BEIVIDE PALACIO, CRISTOBAL CAMARERO COTERILLO, EMILIO CASTILLO VILLAR

01/03/2016

An energy evaluation of data-parallel applications in heterogeneous systems

Comunicación a Congreso

Proceedings of the 16th International Conference on Computational and Mathematical Methods in Science and Engineering, CMMSE 2016

Autoría: BORJA PEREZ PAVON, ESTEBAN STAFFORD FERNANDEZ, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO

2016

Analyzing the Impact of Parallel Programming Models in NoCs of Forthcoming CMP Architectures

Comunicación a Congreso

Proceedings of the EMerging Technology (EMiT) Conference 2016

Autoría: IVAN PEREZ GALLARDO, EMILIO CASTILLO, JULIO RAMON BEIVIDE PALACIO, ENRIQUE VALLEJO GUTIERREZ, JOSÉ LUIS BOSQUE ORERO, MIKEL MORETÓ, MARC CASAS, MATEO VALERO

2016

Energy Efficiency Evaluation in Heterogeneous Computers

Comunicación a Congreso

Proceedings of the EMerging Technology (EMiT) Conference 2016

Autoría: BORJA PEREZ PAVON, JOSÉ LUIS BOSQUE ORERO, ESTEBAN STAFFORD FERNANDEZ, JULIO RAMON BEIVIDE PALACIO

2016

Synthetic Traffic Model of the Graph500 Communications

Comunicación a Congreso

Algorithms and Architectures for Parallel Processing

Autoría: PABLO FUENTES SAEZ, ENRIQUE VALLEJO GUTIERREZ, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO, ANDREEA ANGHE, GERMÁN RODRÍGUEZ, MITCH GUSAT, CYRIEL MINKENBERG

2016

CATA: Criticality Aware Task Acceleration for Multicore Processors

Comunicación a Congreso

2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016)

Autoría: EMILIO CASTILLO, MIQUEL MORETO, MARC CASAS, LLUC ÁLVAREZ, ENRIQUE VALLEJO GUTIERREZ, KALLIA CHRONAKI, ROSA BADIA, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO, EDUARD AYGUADE, JESÚS LABARTA, MATEO VALERO

2016

Simplifying Programming and Load Balancing of Data Parallel Applications on Heterogeneous systems

Comunicación a Congreso

Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit

Autoría: BORJA PEREZ PAVON, JOSÉ LUIS BOSQUE ORERO, JULIO RAMON BEIVIDE PALACIO

2016

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Portal del personal investigador

Detalle Investigador

JOSÉ LUIS BOSQUE ORERO

EngineCL: Usability and Performance in Heterogeneous Computing

Improving utilization of heterogeneous clusters

Load balancing in a heterogeneous world: CPU-Xeon Phi co-execution of data-parallel kernels

Auto-tuned OpenCL kernel co-execution in OmpSs for heterogeneous systems

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL

Simulation with skeletons of applications using dimemas

EngineCL: Usability and Performance in Heterogeneous Computing

Architectural Support for Task Dependence Management with Flexible Software Scheduling

Analysis of load balancing methods over offload model in Intel Xeon Phi

First Steps Towards CPU, GPU, and FPGA Parallel Execution with EngineCL

A clustering-based knowledge discovery process for data centre infrastructure management

Energy efficiency of load balancing for data-parallel applications in heterogeneous systems

A scalable synthetic traffic model of Graph500 for computer networks analysis

To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy

Extending OmpSs for OpenCL Kernel Co-Execution in Heterogeneous Systems

Towards co-execution of massive data-parallel OpenCL kernels on CPU and Intel Xeon Phi

To distribute or not to distribute : the question of load balancing for performance or energy

Assessing the Suitability of King Topologies for Interconnection Networks

An energy evaluation of data-parallel applications in heterogeneous systems

Analyzing the Impact of Parallel Programming Models in NoCs of Forthcoming CMP Architectures

Energy Efficiency Evaluation in Heterogeneous Computers

Synthetic Traffic Model of the Graph500 Communications

CATA: Criticality Aware Task Acceleration for Multicore Processors

Simplifying Programming and Load Balancing of Data Parallel Applications on Heterogeneous systems

EUROCC: NATIONAL COMPETENCE CENTRES IN THE FRAMEWORK OF EUROHPC

REDES DE INTERCONEXIÓN, ACELERADORES HARDWARE Y OPTIMIZACIÓN DE APLICACIONES. Proyecto PID2019-105660RB-C22 financiado por MCIN/ AEI /10.13039/501100011033

REDES DE INTERCONEXIÓN Y SISTEMAS HETEROGÉNEOS (TIN2016-76635-C2-2-R) (AEI/FEDER, UE)

MONT BLANC 3: EUROPEAN SCALABLE AND POWER EFFICIENT HPC PLATFORM BASED ON LOW-POWER EMBEDDED TECHNOLOGY

MONT BLANC 2: EUROPEAN SCALABLE AND POWER EFFICIENT HPC PLATFORM BASED ON LOW-POWER EMBEDDED TECHNOLOGY

MONTBLANC, EUROPEAN SCALABLE AND POWER EFFICIENT HPC PLATFORM BASED ON LOW-POWER EMBEDDED TECHNOLOGY

ARQUITECTURAS DE INTERCONEXIÓN Y APLICACIONES (TIN2013-46957-C2-2-P) (MINECO)

INVESTIGACIÓN APLICABLE AL DISEÑO Y EVALUACIÓN DE REDES DE INTERCONEXIÓN (IADERI)

REALIZACIÓN DEL CURSO TITULADO "DISEÑO DE TIEMPO REAL"

Soporte para co-ejecución eficiente en sistemas heterogéneos

Topologías King como Redes de Interconexión